DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 355

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

8.2
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a
set of register information that is stored in an on-chip RAM to the corresponding DTC registers
and transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to G (DTCERA to DTCERG)
• DTC vector register (DTVECR)
8.2.1
MRA selects the DTC operating mode.
Bit
7
6
5
4
Bit Name
SM1
SM0
DM1
DM0
Register Descriptions
DTC Mode Register A (MRA)
Initial Value
Undefined
Undefined
Undefined
Undefined
R/W
−
−
−
−
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0×: SAR is fixed
10: SAR is incremented after a transfer
11: SAR is decremented after a transfer
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0×: DAR is fixed
10: DAR is incremented after a transfer
11: DAR is decremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
Section 8 Data Transfer Controller (DTC)
Rev.6.00 Mar. 18, 2009 Page 295 of 980
REJ09B0050-0600