DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 683

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

14.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
14.10.5 Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
14.10.6 Restrictions on Use of DMAC or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
• When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant
input until at least five φ clock cycles after TDR is updated by the DMAC or DTC. Abnormal
operation may occur if the transmit clock is input within 4 φ clocks after TDR is updated.
(figure 14.35)
SCI receive-data-full interrupt (RXI).
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.
Figure 14.35 Example of Synchronous Transmission Using DTC
t
LSB
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Section 14 Serial Communication Interface (SCI, IrDA)
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Rev.6.00 Mar. 18, 2009 Page 623 of 980
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