DF2367VF33 Renesas Electronics America, DF2367VF33 Datasheet - Page 300

• Manufacturer Part Number: DF2367VF33
• Description: MCU 3V 384K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VF33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VF33; HD64F2367VF33

Section 7 DMA Controller (DMAC)
7.3.7
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
In short address mode, the TEND pin is only available for channel B. The transfer end signal
indicates the transfer cycle in which the transfer counter has become 0 regardless of the transfer
source. Note however that the transfer end signal exceptionally indicates the transfer cycle in
which the block counter has become 0 in block transfer mode.
Rev.6.00 Mar. 18, 2009 Page 240 of 980
REJ09B0050-0600
Bit
7, 6
5
4
3
to
0
Bit Name
⎯
TEE1
TEE0
⎯
DMA Terminal Control Register (DMATCR)
Initial Value
All 0
0
0
0
R/W
⎯
R/W
R/W
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Transfer End Enable 1
Enables or disables transfer end pin 1
(TEND1) output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
Transfer End Enable 0
Enables or disables transfer end pin 0
(TEND0) output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
Reserved
These bits are always read as 0 and cannot be
modified.