peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 65

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

PEB 3456 E
Functional Description
be stored in the receive data section and to compare this with the length of the requested
data transfer.
In case that the requested transfer length from the receive buffer fits into the provided
data section the data management unit transfers the data block to system memory in one
single burst. If the requested transfer length exceeds the available space of the data
section the transfer is divided into two or more parts. Data packets are written to the data
section until the given data section is filled or the end of a packet is reached.
If the data section in the shared memory is completely filled with data, the data
management unit updates the status word of the receive descriptor by setting the
complete (C) bit and the number of bytes (BNO), which are stored in the data section. In
this case the number of bytes written to the data section equals the size of the data
section.
If the data packet, which is written to system memory, contains the remaining part of a
completely received packet, the data management unit updates the status word of the
receive descriptor by setting the complete bit together with the frame end (FE) bit. The
BNO field is updated on the actual value of bytes written to the data section. If enabled,
the data management unit generates a ‘Frame End’ channel interrupt vector.
With the next receive buffer request the data management unit branches to the next
receive descriptor, which was referenced in the next descriptor field of the current
processed descriptor. To keep track of the linked list the data management unit provides
the possibility to issue a ‘Receive Host Initiated’ interrupt vector, which is generated after
the status word was updated. To enable this interrupt vector the bit RHI must be set in a
descriptor.
Descriptor hold operation
Processing of the descriptor list is controlled by the HOLD bit, which is located in the first
DWORD of each receive descriptor. The HOLD bit indicates that the marked descriptor
is the last descriptor containing a valid data buffer. The data management unit will not
branch to a next descriptor until the hold condition is removed or a ‘Receive Abort’
command forces the TE3-CHATT to branch to the beginning of a new linked list. Since
the HOLD bit marks the last descriptor in a linked list, it may prevent that further received
data packets can be written to system memory.
When a given data section is filled, and does not contain the end of a frame (frame based
protocols) and the requested transfer length could not be satisfied, the data
management unit polls the HOLD bit of the current receive descriptor once more. If the
HOLD bit is removed, it branches to the next descriptor. When the HOLD bit is still ’1’,
an internal poll bit is set and the data management unit does not branch to the next
descriptor. Additionally a ’Hold Caused Receive Abort’ interrupt vector is generated. The
status of the descriptor in the shared memory is aborted (RAB bit set) and the complete
bit and the frame end bit are set in the receive descriptor. The rest of the frame will be
discarded. As long as the HOLD bit remains set further data of the same channel is
Data Sheet
65
05.2001