peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 281

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Access
Address
Reset Value
This register provides the interrupt mask for DS3 status interrupts and DS3 loopback
code interrupts. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see
SEC
CLKS
AISS
REDS
LOSS
D3RIMSK
DS3 Receive Interrupt Mask Register
The following definition applies:
1
0
RSDL
TSDL
LPCS
N
AIC
XBIT
IDLES
FAS
Data Sheet
r
15
0
“Layer One Interrupts” on Page
0
0
: read/write
: 1C8
: 1FFF
The corresponding interrupt vector will not be generated by the device.
The corresponding interrupt vector will be generated.
Mask ’Receive Spare Data Link Transfer Buffer Full’
Mask ’Transmit Spare Data Link Transfer Buffer Empty’
Mask ’Loopback Code Status’ (flagged in D3RLPCS)
Mask ’1 Second Interrupt’
Mask ’DS3 Clock Status’
Mask ’N
Mask ’AIC-bit Image’ (C-bit parity mode)
Mask ’X-bit Image’
Mask ’DS3 Idle Signal State’
Mask ’DS3 Alarm Indication Signal State’
Mask ’DS3 Red Alarm State’
Mask ’DS3 Input Signal State’
Mask ’Frame Alignment State’
CLKS RSDL TSDL LPCS SEC
12
H
H
(PCI), 64
r
11
-bit Image’ (C-bit parity mode only)
10
H
(Local bus)
9
137.
8
281
N
7
r
AIC
6
XBIT IDLES AISS REDS LOSS FAS
5
4
Register Description
3
2
PEB 3456 E
1
05.2001
0