peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 308

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

8.9.3
TUTCFG
Test Unit Transmit Configuration Register
Access
Address
Reset Value
INV
FBT
LEN
ZS
MD
Data Sheet
15
0
0
Test Unit Registers
INV
13
: read/write
: 280
: 0000
Invert output
This bit enables inversion of the test unit output. Bit inversion is done
after the zero suppression insertion point.
0
1
Feedback Tap
This bit field sets the feedback tap in pseudorandom pattern mode.
PRBS shift register input bit 0 is XOR of shift register bits LEN and FBT.
Pattern Generator Length
This bit field sets the pattern generator length to 1..32.
Enable Zero Suppression
This bit enables zero suppression where a ’1’ bit is inserted at the output
if the next 14 bits in the shift register are ’0’.
0
1
Generator Mode
This bit selects the generator mode of the test unit to be either PRBS or
fixed pattern mode.
0
1
12
H
H
(PCI), C0
No inversion
Invert pattern generator output
No zero suppression
Zero suppression.
Pseudorandom Pattern (PRBS)
Fixed Pattern
FBT(4:0)
H
(Local bus)
8
308
0
6
LEN(4:0)
Register Description
2
PEB 3456 E
ZS
1
05.2001
MD
0