peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 247

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

WSE
8.9.2
FCONF
Framer and FDL Configuration Register
Access
Address
Reset Value
IIP
MBID
Data Sheet
IIP
15
14
0
PCI and Local Bus Slave Register Set
0
: read/write
: 100
: 8080
Initialization in Progress (Read Only)
After reset (hardware reset or software reset) the internal RAM’s are self
initialized by the TE3-CHATT. During this time (approx. 250 s) no other
accesses to the device than reading register CONF1 or FCONF are
allowed. This bit must be polled until it has been deasserted by the TE3-
CHATT.
0
1
Mailbox Interrupt Vector Disable
0
1
Wait State Enable
This bit enables the wait state controlled master mode.
0
1
0
H
H
(PCI), 00
Self initialization has finished.
Self initialization in progress.
Enable generation of mailbox interrupt vectors. As soon as
system software on PCI side writes to register MBP2E0 an
interrupt vector indicating a mailbox interrupt will be forwarded to
the internal interrupt FIFO and can be read by the local CPU.
Disable generation of mailbox interrupt vectors.
LRDY (Intel), LDTACK (Motorola) controlled bus mode.
Wait state controlled bus mode. Wait states are defined in
register MTIMER.WS.
0
0
H
(Local Bus)
0
0
247
MBID WSE BSD
7
6
5
P28
4
Register Description
P18
3
P08
2
PEB 3456 E
LAE LME
1
05.2001
0