peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 319

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

TURSTAT
Test Unit Receive Status Register
Access
Address
Reset Value
INV
LA1
LA0
LOOS
EMI
LBE
A1
Data Sheet
15
0
0
0
: read
: 2B0
: 0021
Inverted Pattern
This bit indicates that the received PRBS sequence is inverted.
0
1
Latched ’Input all ’1’’
This bit indicates that the condition ’Input all ’1’’ was active since last
status register read.
Latched ’Input all ’0’’
This bit indicates that the condition ’Input all ’0’’ was active since last
status register read.
Latched Out of Synchronization
This bit indicates that the receiver was out of synchronization since last
status register read.
End of Measurement Interval
This bit indicates that the end of the measurement internal was reached
since last read of error counter or that command TURCMD.RDC was
given. The results of the bit error rate test are available in register
TURBC0,1 and TUREC0,1. This flag is cleared when the error counter
is read. Counters will not be overwritten while EMI is ’1’.
Latched Bit Error Detected Flag
This bit indicates that at least ’1’ one bit error occurred since last read of
this register. It is cleared by status register read.
Input all ‘1’s
This bit indicates that the input contained all ’1’ during the last 32 bits. It
is reset if at least one ’0’ occurs in 32 bits.
0
H
H
(PCI), D8
Not Inverted.
Inverted.
0
0
H
(Local bus)
0
INVS LA1
8
319
7
LA0 LOOS EMI
6
5
4
Register Description
LBE
3
A1
2
PEB 3456 E
A0
1
05.2001
OOS
0