peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 151

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

address is sent, the data stored in the memory at the selected address is shifted in on
the SPSI pin. The read operation is terminated by setting SPCS high (see Figure 5-3).
•
Figure 5-3
5.2.3
Prior to any attempt to write data to an external EEPROM, the write enable latch must
be set by issuing the WREN instruction. This is done by setting SPCS low and then
clocking out the WREN instruction. After all eight bits of the instruction are transmitted,
the SPCS will be brought high to set the write enable latch.
Once the write enable latch is set, the user may proceed by issuing a write instruction,
followed by the eight bit address and then the data to be written. In order that data will
actually be written to the EEPROM, the SPCS is set high after the least significant bit
(D0) of the data byte has been clocked in. Refer to Figure 5-4 for detailed illustrations
on the byte write sequence. While the write is in progress, the register bit SPI.START
may be read to check the status of the transaction. When a write cycle is completed, the
register bit SPI.START is reset.
•
Figure 5-4
Data Sheet
SPCLK
SPCLK
SPCS
SPSO
SPCS
SPSO
SPSI
SPSI
SPI Write Sequence
SPI Read Sequence
SPI Write Sequence
0
0
0
0
1
0
1
0
2
0
2
0
instruction
instruction
3
0
3
0
4
0
4
0
5
0
5
0
6
1
6
1
7
1
7
0
151
8
8
7
7
9
9
6
6
8 bit address
8 bit address
14 15 16 17 18 19 20 21 22 23
14 15 16 17 18 19 20 21 22 23
0
0
7
7
6
6
Interface Description
5
5
data out
data in
4
4
3
3
PEB 3456 E
2
2
1
1
0
0
05.2001