peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 147

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

signalling environment according to the PCI specification Rev. 2.1.
The PCI bus controller operates as initiator or target. Commands are supported as
follows:
• Master memory read single DWORD/burst of up to 64 DWORDs with zero wait cycles.
• Master memory write single DWORD/burst of up to 64 DWORDs with zero wait cycles.
• Slave memory read single DWORD.
• Slave memory write single DWORD.
Fast back-to-back transfers are provided for slave accesses only. All read/write
accesses to the TE3-CHATT must be 32-bit wide, that is all bytes must be enabled. Non
32-bit accesses result in system interrupt.
Refer also to the PCI specification Rev. 2.1 for detailed information about PCI bus
protocol.
5.1.1
The transaction starts with an address phase which occurs during the first cycle when
FRAME is activated (clock 1 in Figure 5-1). During this phase the bus master (initiator)
5
5.1
A 32-bit and 66 MHz capable PCI bus controller provides the interface between the TE3-
CHATT and the host system. PCI Interface pins are measured as compliant to the 3.3V
outputs a valid address on AD(31:0) and a valid bus command on C/BE (3:0). The first
clock of the first data phase is clock 3. During the data phase C/ BE indicate which byte
lanes on AD(31: 0) are involved in the current data phase.
The first data phase on a read transaction requires a turnaround cycle. In Figure 5-1 the
address is valid on clock 2 and then the master stops driving AD. The target drives the
AD lines following the turnaround when DEVSEL is asserted. (TRDY cannot be driven
until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once
enabled, the AD output buffers of the target stay enabled through the end of the
transaction.
A data phase may consist of a data transfer and wait cycles. A data phase completes
when data is transferred, which occurs when both IRDY and TRDY are asserted. When
either is deasserted a wait cycle is inserted. In the example below, data is successfully
transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The
first data phase completes in the minimum time for a read transaction. The second data
phase is extended on clock 5 because TRDY is deasserted. The last data phase is
extended because IRDY is deasserted on clock 7. The Master knows at clock 7 that the
next data phase is the last. However, the master is not ready to complete the last
Data Sheet
Interface Description
PCI Interface
PCI Read Transaction
147
Interface Description
PEB 3456 E
05.2001