peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 392

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Note: Rise and fall times are specified in terms of the edge rate measured in V/ns. This
9.4.1
•
Figure 9-2
Table 9-5
Parameter
CLK cycle time
CLK high time
CLK low time
CLK slew rate (see note)
•
Figure 9-3
Data Sheet
0.3 V
Clock
Input delay
0.4 V
slew rate must be met across the minimum peak-to-peak portion of the clock
waveform shown in
0.5 V
DD3
DD3
PCI Bus Interface Timing
DD3
PCI Clock Cycle Timing
PCI Clock Characteristics
PCI Input Timing Measurement Conditions
V
V
V
V
th
th
tl
tl
0.6 V
Figure
t
high
DD3
9-3.
Symbol
t
t
t
high
V
cyc
low
t
cyc
test
392
min.
0.2 V
Inputs valid
t
1.5
Limit Values
15
su
6
7
t
low
DD3
V
t
max.
h
test
4
Electrical Characteristics
V
test
V/ns
Unit
ns
ns
ns
0.4 V
(minimum)
PEB 3456 E
DD3
, p-to-p
V
max
05.2001