peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 156

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

5.3.2
5.3.2.1
The demultiplexed bus modes use the local bus port pins LA(12:1) for the 16- bit address
and the local bus port pins LD(15:0) for 16 bit data. A read/write access is initiated by
placing an address on the address bus and asserting LCS0 together with the command
signal LWRRD (see
the signal LDS is asserted. Data is driven onto the data bus either by the TE3-CHATT
(for read cycles) or by the external processor (for write cycles). After a period of time,
which is determined by the access time to the internal registers valid data is placed on
the bus, which is indicated by asserting the active low signal LDTACK.
Note: LCS0 need not be deasserted between two subsequent cycles to the same
Read cycles
Input data can be latched and the data strobe signal can be deactivated now. This
causes the TE3-CHATT to remove its data from the data bus which is then tri-stated
again. LDTACK is driven high and will be tri-stated as soon as LCS0 is deasserted.
Write cycles
The data strobe signal can be deactivated now. If a subsequent bus cycle is required,
the external processor can place the respective address on the address bus.
5.3.2.2
As in Intel mode a read/write access from the PCI bus to the 16 bit demultiplexed local
bus is initiated by accessing the PCI memory space base mapped by the base address
register 2. Each valid read or write access to this base address triggers the local bus
master interface which in turn starts arbitration for the local bus using the interface
signals LBR and LBG and LBGACK. As soon as the TE3-CHATT gets access to the local
bus it places a valid address on the address bus, sets the LSIZE0 signal which indicates
a 8- or 16-bit bus access and asserts the corresponding chip select signal. The signal
LWRRD indicates a read or write operation. The data cycle begins when the signal LDS
is asserted. Data is driven onto the data bus either by the TE3-CHATT or by the external
component.
A transaction is finished on the local bus when the external device asserts the active low
signal LDTACK or when the internal wait state timer expires.
Data Sheet
device.
Motorola Mode
Slave Mode
Master Mode
“Motorola Bus Mode” on Page
156
157). The data cycle begins when
Interface Description
PEB 3456 E
05.2001