peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 290

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Reset Value
D3RCPEC
DS3 Receive Path Parity Error Counter
Access
Address
Reset Value
CPE(15:0)
D3RPEC
DS3 Receive Parity Error Counter
Access
Address
PE(15:0)
Data Sheet
15
15
: read/write
: 1E8
: 0000
Parity Bit Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of parity errors (P-bits in DS3 overhead bits). The P-bit is
duplicated in the DS3 frame structure but only one error is counted per
multiframe. Errors are not counted in out of frame state.
: read/write
: 1EC
: 0000
Path Parity Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of path parity errors (CP bits in DS3 C-bit parity overhead bits).
CP-bits are triplicated in the DS3 frame structure but only single error
maximum is counted per multiframe. Errors are not counted in out of
frame state.
H
H
H
H
(PCI), 74
(PCI), 76
H
H
(Local bus)
(Local bus)
CPE(15:0)
PE(15:0)
290
Register Description
PEB 3456 E
05.2001
0
0