peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 215

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

STOP
CONF1
Configuration Register 1
Access
Address
Reset Value
IIP
SRST
Data Sheet
IIP
31
15
0
0
: read/write
: 040
: 820000F0
Initialization in Progress (Read Only)
After reset (hardware reset or software reset) the internal RAM’s are self
initialized by the TE3-CHATT. During this time (approx. 250 s) no other
accesses to the device than reading register CONF1 or FCONF are
allowed. This bit must be polled until it has been deasserted by the TE3-
CHATT.
0
1
Stop
After reset the TE3-CHATT can be switched to ’Fast Initialization’ mode.
During stop mode internal RAM’s will not be accesses by internal state
machines. This mode is for test purposes only and allows writing or
reading the internal RAM’s.
0
1
Software Reset
This bit issues a software reset to the TE3-CHATT. During software
reset all interfaces except PCI interface are forced into their idle state.
After software reset is set the TE3-CHATT starts its self initialization and
MFL(12:0)
0
H
Self initialization has finished.
Self initialization in progress.
Device is in normal operation. This bit must be set to zero after
chip initialization. See also
Device is in ‘Fast Initialization Mode’. This function is used for test
purposes only.
0
H
0
STOP SRST
25
24
8
215
MBIM PBIM RBIM RFIM SFL RBM LBE 0
23
0
7
“Mode Initialization” on Page
0
6
MFLE
21
5
20
4
Register Description
3
MFL(12:0)
2
PEB 3456 E
1
05.2001
Dev
170.
16
0