peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 16

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

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List of Figures
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Figure 8-27
Figure 8-28
Figure 9-1
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Figure 9-9
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Data Sheet
215
T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 215
T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 215
T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
T1/E1 Test Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Framer, M13 and Facility Data Link and Mailbox Interrupt Notification . . .
Test Unit Access Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Port configuration in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Local Port Loops in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Test Breakout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
TE3-CHATT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
TE3-CHATT Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
System Integration of the TE3-CHATT . . . . . . . . . . . . . . . . . . . . . . . 215
TE3-CHATT Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DS3 Transmit Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 391
PCI Clock Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
PCI Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . 392
PCI Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . 393
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Intel Read Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . 395
Intel Write Cycle Timing (Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . 395
Intel Read Cycle Timing (Master Mode, LRDY controlled) . . . . . . . . 397
Intel Write Cycle Timing (Master Mode, LRDY controlled). . . . . . . . . 397
Intel Read Cycle Timing (Master Mode, Wait state controlled) . . . . . 398
Intel Write Cycle Timing (Master Mode, Wait state controlled) . . . . . 398
Intel Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Motorola Read Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . 400
Motorola Write Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . 400
Motorola Read Cycle Timing (Master Mode, LDTACK controlled). . . 402
Motorola Write Cycle Timing (Master Mode, LDTACK controlled). . . 402
Motorola Read Cycle Timing (Master Mode, Wait state controlled). . 403
Motorola Write Cycle Timing (Master Mode, Wait state controlled) . . 403
Motorola Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
16
PEB 3456 E
05.2001
Page