peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 185

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

DPED
RTA
SE
PER
BM
MS
Data Sheet
Received Target Abort
This bit will be set whenever a transaction in which the TE3-CHATT
acted as bus master was terminated with target abort.
0
1
Data Parity Error Detected
0
1
SERR Enable
This bit enables assertion of SERR in case of severe system errors.
0
1
Parity Error Response
This bit enables reporting of parity errors via pin PERR.
0
1
Bus Master
This bit controls a device ability to act as a master on PCI bus.
0
1
Memory Space
This bit controls the device response to memory space accesses.
0
1
No target abort detected.
Transaction terminated with target abort. This bit will be cleared
by writing a ‘1’ to this bit.
No data parity error detected.
The following three conditions are met:
•The bus agent asserted PERR itself or observed PERR
•The bus agent acted as bus master for the operation in which the
•The Parity Error Response Bit is set
Assertion of SERR disabled.
Enables report of
•Address parity errors
•Master abort
•Target abort
Assertion of PERR disabled.
Enables the assertion of PERR. See also Data Parity Error
Detected.
Disables the device from generating PCI accesses.
Allows the device to act as bus master.
Response to memory space accesses disabled.
Allows a device to respond to memory space accesses.
asserted.
error occurred.
185
Register Description
PEB 3456 E
05.2001