peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 23

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

• Estimated power consumption: 2W
• Also available as device with extended temperature range -40..+85 C
1.1.1
• Multiplexing/Demultiplexing of four asynchronous DS1 bit streams into/from M13
• Multiplexing/Demultiplexing of 3 E1 signals into/from ITU G.747 compliant DS2 signal.
• DS2 line loopback detection/generation
• Framing according to ANSI T1.107, T1.107a or ITU-T G.747
• Insertion and extraction of X-bit
• Insertion and Extraction of alarms (remote alarm, AIS)
• Detection of AIS in presence of BER 10
• Alarm and performance monitoring (framing bit errors, parity errors)
• Reframe time below 7ms (TR-TSY-000009) for DS2 format and below 1 ms for ITU
• Bit Stuffing/Destuffing in M12 multiplex format or C-bit parity format
1.1.2
• Multiplexing/demultiplexing of seven DS2 into/from M13 asynchronous format
• Multiplexing/demultiplexing of seven DS2 into/from C-bit parity format according to
• DS3 framing according to ANSI T1.107, T1.107a, ITU-T G.704
• Support of unipolar and B3ZS encoded signals
• Provides access to the DS3 overhead bits and the DS3 stuffing bits via a serial clock
• Insertion and Extraction of alarms according to ANSI T1.404 (remote alarm, AIS, far
• Supports HDLC (Path Maintenance Data Link) and bit oriented message mode (Far
• Detection of AIS and idle signal in presence of BER 10
• Detection of excessive zeroes and LOS
• Alarm and performance monitoring with 16-bit counters for line code violations,
• Automatic insertion of severely errored frame and AIS defect indication
• Full scan path and BIST of on-chip RAMs for production test
• Performance: 45Mbit/s (DS3) throughput per direction
Data Sheet
asynchronous format
G.747 format
according to ANSI T1.107, ANSI T1.107a
ANSI T1.107, ITU-T G.704
and data interface (overhead interface)
end receive failure)
End Alarm and Control Channel) in C-bit parity mode. An integrated signalling
controller provides 2x32 byte deep FIFO’s for each direction of both channels
excessive zeroes, parity error (P-bit), framing errors (F-bit errors with or without M-bit
errors, far end block error (FEBE-bit) and CP-bit errors.
M12 Multiplexer and DS2 Framer
M23 Multiplexer and DS3 Framer
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23
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TE3-CHATT Overview
PEB 3456 E
05.2001