peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 240

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

SIQL
SIQBA
Q
Data Sheet
Set Interrupt Queue Length
This bit field enables setup of the interrupt queue length of queue Q. The
value to be programmed has to be configured via register IQL prior to a
write access to this bit.
0
1
Set Interrupt Queue Base address
This bit field enables setup of the interrupt queue base address of queue
Q. The value to be programmed has to be configured via register IQBA
prior to a write access to this bit.
0
1
Interrupt Queue Number
This bit field determines the interrupt queue number for which
programming is valid. The first eight (0..7) interrupt queues are used for
channel, port and system interrupt vectors, while the last interrupt queue
(8) is used for command interrupt vectors. Interrupt queue number seven
is per default the high priority interrupt queue.
System software may setup the interrupt queue high priority mask, the
interrupt queue length and the interrupt queue base address
simultaneously by setting SIQL, SIQBA and SIQM.
The command interrupt queue has a fixed length of two times 256
DWORDs, that is one DWORD for each interrupt vector.
It is possible to setup the interrupt queue high priority mask, the interrupt
queue length and the interrupt queue base address concurrently by
setting SIQBA, SIQL and SIQM to ’1’.
Note: Programming of interrupt queue length or interrupt queue high
Note: Programming of interrupt queue high priority mask is not valid for
0..8
No operation
Set interrupt queue length.
No operation
Update interrupt queue base address with value programmed in
register IQBA.
priority mask is not valid for the command interrupt queue
(interrupt queue 8).
the high priority interrupt queue (interrupt queue 7).
Interrupt Queue
240
Register Description
PEB 3456 E
05.2001