peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 170

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

bit CONF1.SRST. During software reset all interfaces except PCI interface are forced
into their idle state. After software reset is set the TE3-CHATT starts its self initialization
and IIP will be asserted. Chip initialization is finished when CONF1.IIP is deasserted.
Afterwards the software reset bit must be set to ‘0’ to allow further operation.
The M13 multiplexer, DS3/DS2 framer mode, T1/E1 framer mode and the DS1/E1 and
DS3 port interface has to be programmed. It is assumed, that the DS3 port clock and
CTCLK are active. The T1/E1 ports shall be disabled, thus no incoming data is forwarded
to the time slot assigner and to the T1/E1 framer.
Transmit direction
The T1/E1s have to be enabled via register XPI.TEN. After the tributaries are enabled,
the F-Bit (T1 mode) respectively time slot zero (E1 mode) are generated by the on-chip
T1/E1 framer and the signalling controller. To synchronize the first bit of a frame to an
external reference the common transmit frame synchronization pulse CTFS can be used
(in external timing mode only). After a tributary has been enabled, payload data is
provided from the time slot assigner. Since the time slot assignment is in reset state, that
is all time slots are set to inhibit, data bits are sent as ‘1’.
Receive direction
The tributaries have to be enabled via register XPI.REN. After they are enabled, the on-
chip T1/E1 framer tries to achieve frame alignment. As soon as frame alignment has
been achieved, incoming payload data is passed to the time slot assigner. Since time
slot assignment is in reset state, that is all time slots are set to inhibit, data bits are
discarded.
their initialization in progress signal. The register bit CONF1.IIP is the result of all signals.
As soon as all internal modules have finished their RAM initialization the register bit
CONF1.IIP is deasserted. Software must poll the register bit CONF1.IIP until this bit has
been deasserted. Read access to registers other than CONF1 is prohibited and may
result in unexpected behavior of the design. Write accesses are not allowed.
Chip initialization is finished when CONF1.IIP is ‘0’.
Software Reset
Alternately the TE3-CHATT provides the capability to issue a software reset via register
7.2
After chip initialization is finished the system software has to setup the device for the
required function.
The system software has to poll bit CONF1.IIP (FCONF.IIP). As soon as CONF1.IIP is
deasserted, the system software has to clear bit CONF1.STOP and has to set the
general operating modes in register CONF1.
Data Sheet
Mode Initialization
170
Reset and Initialization procedure
PEB 3456 E
05.2001