peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 37

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
AC24
AB24
AA23
Pin No.
LRD
or
LDS
LWR
or
LRDWR
LRDY
or
DTACK
Symbol
Output (O)
Input (I)
I/O
I/O
I/O
I/O
I/O
I/O
37
Read (Intel Bus Mode)
This active low signal selects a read
transaction.
Data strobe (Motorola Bus Mode)
This active low signal indicates that valid
data has to be placed on the data bus
(read cycle) or that valid data has been
placed on the data bus (write cycle).
Write Enable (Intel Bus Mode)
This active low signal selects a write
cycle.
Read Write Signal (Motorola Bus
Mode)
This input signal distinguishes write from
read operations.
Ready (Intel bus mode)
This signal indicates that the current bus
cycle is complete. The TE3-CHATT
asserts LRDY during a read cycle if valid
output data has been placed on the data
bus. In write direction LRDY will be
asserted when input data has been
latched.
In local bus master mode TE3-CHATT
evaluates LRDY to finish a transaction.
Data Transfer Acknowledge (Motorola
bus mode)
This active low input indicates that a data
transfer may be performed. During a read
cycle data becomes valid at the falling
edge of DTACK. The data is latched
internally and the bus cycle is terminated.
During a write cycle the falling edge of
DTACK marks the latching of data and the
bus cycle is terminated.
Function
Pin Description
PEB 3456 E
05.2001