peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 321

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Address
Reset Value
BC(31:0)
TURBC0
Test Unit Receive Bit Counter Low Word
Access
Address
Reset Value
BC(31:0)
TURBC1
Test Unit Receive Bit Counter High Word
Access
Data Sheet
15
15
: read
: 2B4
: 0000
Bit Counter
See description below.
: read
: 2B8
: 0000
Bit Counter
BC is a 32 bit counter which is split between two 16 bits registers. It
counts receive clock slots when the receiver is enabled. Bits are counted
in a background register which is not directly readable. The values are
transferred to the two 16 bit foreground (readable) registers and cleared
in one of the two ways:
1. Assert command TURCOM.RDC.
2. Automatically at end of measurement interval.
The background register is transferred to the foreground register and
cleared in the same way as the bit error counter (see previous section).
H
H
H
H
(PCI), DA
(PCI), DC
H
H
(Local bus)
(Local bus)
BC(31:16)
BC(15:0)
321
Register Description
PEB 3456 E
05.2001
0
0