peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 195

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

MW
MRL
MR
MEM
PCI Memory Command Register
Access
Address
Reset Value
BAR2
Data Sheet
31
15
0
0
30
0
0
0
0
: read/write
: 48
: 000007E6
Enable Base Address Register 2
Setting this bit enables Base Address Register 2. Per default base
address register two is disabled. If an EEPROM is connected to the SPI
interface the value of this bit can be loaded via the EEPROM.
Additionally this bit can set using standard PCI configuration write
commands.
0
1
Memory Write Command
The value of this register contains the write command to be used during
initiator transfers and is set to memory write after reset. The value of this
register is configurable during setup of the bridge either by loading the
value from EEPROM or by writing from PCI side.
Memory Read Command (Long transfers)
The value of this register defines command to be used for read transfers
which are equal or more than two DWORDs and is set to memory read
line after reset. The value of this register is configurable during run time
of the bridge either by loading the value from EEPROM or by writing from
PCI side.
Memory Read Command
The value of this register defines command to be used for read transfers
of single DWORDs.The value of this register is configurable during run
0
0
H
Base Address Register 2 is disabled.
Base Address Register 2 is enabled.
11
0
H
MW(3:0)
0
0
0
8
195
0
7
MRL(3:0)
0
0
0
4
Register Description
0
3
MR(3:0)
0
PEB 3456 E
BAR2
17
05.2001
16
0
0