peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 101

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

format is enabled).
Setting a code word in bit field FMR0.SIM initiates alarm simulation. Error counting and
Alarm Simulation
Alarm simulation does not affect the normal operation of the device, i.e. all channels
remain available for transmission. However, possible ‘real’ alarm conditions are not
reported to the processor or to the remote end when the device is in the alarm simulation
mode.
The alarm simulation is initiated by setting different code words in bit field FMR0.SIM.
The following alarms are simulated:
• Loss of Signal
• Alarm Indication Signal (AIS)
• Auxiliary pattern
• Loss of pulse frame
• Remote alarm indication
• Framing error counter
• CRC-4 error counter
• E-Bit error counter
Some of the above indications are only simulated if the TE3-CHATT is configured in a
mode where the alarm is applicable (e.g. no CRC-4 error simulation when doubleframe
indication will occurs while this bit is set. After it is reset all simulated error conditions
disappear.
4.8
The signalling controller provides access to the data link and S
and provides access to the far end alarm and control channel (FEAC) and the C-bit parity
path maintenance data link channel. It operates in HDLC, BOM or automatic modes.
4.8.1
In HDLC mode the transmit signaling controller of the TE3-CHATT performs the FLAG
generation, CRC generation, zero bit-stuffing and programmable IDLE code generation.
Buffering of transmit data is done in the 2x32 byte deep transmit FIFO. The signaling
information will be internally multiplexed with the data applied to the outgoing ports and
is inserted in or extracted from the DL-Bits in T1 ESF mode or the S
Any sequence of S
Shared Flags
The closing flag of a previously transmitted frame simultaneously becomes the opening
flag of the following frame if there is one to be transmitted. The Shared Flag feature is
enabled by setting XCR1.SF.
Data Sheet
Signaling Controller Protocol Modes
HDLC Mode
a
-bits can be specified for protocol insertion.
101
a
Functional Description
bits of the T1/E1 signals
a
-bits in E1 modes.
PEB 3456 E
05.2001