peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 152

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

system clock as clock reference for the local microprocessor interface. The local bus
master capability allows to access peripherals located on the local bus via the PCI
interface. Bit FCONF.LME enables the bus master capability.
The base address register two is disabled per default and can be enabled during start-
configuration space.
The TE3-CHATT supports a maximum of three 8 kByte pages of memory on the local
address bus. The correspondence between the accessed PCI memory space (mapped
via base address register 2) and the asserted chip selects is shown in table 5-1. The
mapping of the PCI byte enables to the local bus address is dependent on the selected
bus mode and is explained in detail in the corresponding section.
Table 5-1
5.3
The Local Microprocessor Interface is a demultiplexed switchable Intel or Motorola style
interface with master and slave functionality. In slave mode it is used to operate the M13
multiplexer, DS3/DS2 framer, T1/E1 framer and the facility data link of the TE3-CHATT.
The TE3-CHATT provides a local clock output LCLK, which is a feed through of the PCI
up of the internal PCI interface. This is done by setting bit MEM.BAR2 in the PCI
Data Sheet
Page
0
1
2
3
Local Microprocessor Interface
Correspondence between PCI memory space and chip select
0000
2000
4000
6000
AD(14:0)
H
H
H
H
- 1FFF
- 3FFF
- 5FFF
- 7FFF
H
H
H
H
152
LCS2
1
0
0
Not valid
LCS1
0
1
0
Interface Description
PEB 3456 E
05.2001