peb3456 Infineon Technologies Corporation, peb3456 Datasheet - Page 105

• Manufacturer Part Number: peb3456
• Description: Channelized T3 Termination With Ds3 Framer, M13 Multiplexer, T1/ E1 Framers And 256 Channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

During the basic frame asynchronous state updating of register RSAW4 and interrupt
vector generation is disabled. In CRC-4 multiframe format the detection of the S
combinations can be done either synchronous or asynchronous to the submultiframe. In
synchronous detection mode updating of register RSAW4 is done in the multiframe
synch. state. In asynchronous detection mode updating is independent to the multiframe
synchronous state.
S
The S
sequence 0001
selectable S
the TE via S
The S
sequence 0010
selectable S
reference points are reported via S
synchronous state.
4.8.5
Access to the FIFO’s of the signalling controllers is handled via registers RFF and XFF.
FIFO status and commands are exchanged using the port status registers PSR and the
handshake register HND. Additional facility data link interrupt vectors inform system
software about protocol and FIFO status.
Receive FIFO
In receive direction there are different interrupt indications associated with the reception
of data:
• A ’Receive Pool Full’ (RPF) interrupt vector is indicating that a data block can be read
• A ’Receive Message End’ (RME) interrupt vector is indicating that the reception of one
Data Sheet
a
-bit Error Indication Counters
from the receive FIFO and the received message is not yet complete. It is generated,
when the amount of data bytes has reached the programmed threshold.
message is completed. After this interrupt system software has to read the PSR
register in order to get the number of bytes stored in the receive FIFO. This number
includes the status byte which is written into the receive FIFO as the last byte after the
received frame. The status byte includes information about the CRC result, valid
frame indication, abort sequence or data overflow. The format of the status byte is
shown in the table below:
SMODE(1:0) BRFO
7
a
a
-bit error indication counter CRC1 (16 bits) counts either the received bit
-bit error indication counter CRC2 (16 bits) counts either the received bit
Signalling Controller FIFO Operations
6
a
a6
a
-bit. In the primary rate access digital section CRC errors are reported from
-bit. In the primary rate access digital section CRC errors detected at T-
. Incrementing is only possible in the multiframe synchronous state.
B
B
5
or 0011
or 0011
4
B
B
or user programmable values in every submultiframe on a
or user programmable values in every submultiframe on a
STAT(4:0)
a6
. Incrementing is only possible in the multiframe
105
0
Functional Description
PEB 3456 E
05.2001
a
-bit