ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 86

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Digital Signal Processing Block
Figure 2–53. DSP Block Interface to Interconnect
2–78
Arria GX Device Handbook, Volume 1
C4 Interconnect
LAB
18
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
36
16
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed and unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface. The LAB row source for control
signals, data inputs, and outputs is shown in
Row Interface
36
12
Block
36 Inputs per Row
R4 Interconnect
16
Control
A[17..0]
B[17..0]
DSP Block
Row Structure
OA[17..0]
OB[17..0]
36 Outputs per Row
Direct Link Outputs
to Adjacent LABs
36
36
Table
2–15.
Altera Corporation
Direct Link Interconnect
from Adjacent LAB
May 2008
LAB