ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 72

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

TriMatrix Memory
Figure 2–44. M4K RAM Block Control Signals
2–64
Arria GX Device Handbook, Volume 1
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
■
■
■
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
M4K RAM blocks allow for different clocks on their inputs and outputs.
Either of the two clocks feeding the block can clock M4K RAM block
registers (renwe, address, byte enable, datain, and output
registers). Only the output register can be bypassed. The six labclk
signals or local interconnects can drive the control signals for the A and B
ports of the M4K RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals, as shown in
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
6
FIFO
ROM
Shift register
clock_a
clock_b
clocken_a
clocken_b
Figure
2–44.
renwe_a
renwe_b
Altera Corporation
aclr_a
May 2008
aclr_b