ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 56

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Adaptive Logic Modules
2–48
Arria GX Device Handbook, Volume 1
Figure 2–35. Conditional Operation Example
Arithmetic mode also offers clock enable, counter enable, synchronous
up/down control, add/subtract control, synchronous clear, and
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals may be used for the inputs that are
shared between the four LUTs in the ALM. The synchronous clear and
synchronous load options are LAB-wide signals that affect all registers in
the LAB. The Quartus II software automatically places any registers that
are not used by the counter into other LABs.
Carry Chain
Carry chain provides a fast carry function between the dedicated adders
in arithmetic or shared arithmetic mode. Carry chains can begin in either
the first ALM or the fifth ALM in a LAB. The final carry-out signal is
routed to an ALM, where it is fed to local, row, or column interconnects.
Carry Chain
syncdata
X[0]
X[1]
X[2]
Y[0]
Y[1]
Y[2]
ALM 1
ALM 2
Comb &
Comb &
Comb &
Comb &
Adder
Adder
Adder
Adder
Logic
Logic
Logic
Logic
X[2]
X[1]
X[0]
Adder output
is not used.
syncload
syncload
syncload
D
D
D
reg0
reg1
reg0
carry_out
Q
Q
Q
R[0]
R[1]
R[2]
Altera Corporation
To general or
local routing
To general or
local routing
To general or
local routing
To local routing &
then to LAB-wide
syncload
May 2008