ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 119

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–75. Arria GX IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
(3)
Altera Corporation
May 2008
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–75:
clkout
aclr/apreset
sclr/spreset
ce_out
oe
Chip-Wide Reset
Output Register
Output Register
OE Register
OE Register
ENA
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
ENA
ENA
ENA
Q
Q
Q
Q
Notes
Used for
DDR, DDR2
SDRAM
clk
(1),
Open-Drain Output
Arria GX Device Handbook, Volume 1
(2)
Drive Strength
Pin Delay
Output
Control
OE Register
t CO Delay
V CCIO
Arria GX Architecture
V CCIO
PCI Clamp (3)
Termination
On-Chip
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
2–111