ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 33

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
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The byte ordering at the receiver output might be different than what was
transmitted. This is a non-deterministic swap, because it depends on PLL
lock times and link delay. If required, you must implement byte ordering
logic in the PLD to correct this situation.
For more details, refer to the
volume 2 of Arria GX Device Handbook.
Receiver Phase Compensation FIFO Buffer
A receiver phase compensation FIFO buffer is located at each receiver
channel’s logic array interface. It compensates for the phase difference
between the receiver PCS clock and the local PLD receiver clock. The
receiver phase compensation FIFO is used in all supported functional
modes. The receiver phase compensation FIFO buffer is eight words deep
in PCI Express (PIPE) mode and four words deep in all other modes.
For more details about architecture and clocking, refer to the
Transceiver Architecture
Loopback Modes
Arria GX transceivers support the following loopback configurations for
diagnostic purposes:
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Serial loopback
Reverse serial loopback
Reverse serial loopback (pre-CDR)
PCI Express (PIPE) reverse parallel loopback (available only in
[PIPE] mode)
chapter in volume 2 of Arria GX Device Handbook.
Arria GX Transceiver Architecture
Arria GX Device Handbook, Volume 1
Arria GX Architecture
Arria GX
chapter in
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