ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 117

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–73. Arria GX IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
May 2008
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
DQS Local
2–73:
Bus (2)
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
Input Register
Input Register
D
CLRN/PRN
ENA
CLRN/PRN
D
ENA
Input RegisterDelay
I
nput Pin to
Note (1)
Q
Q
D
ENA
CLRN/PRN
Arria GX Device Handbook, Volume 1
To DQS Logic
Latch
Block (3)
Q
VCCIO
Arria GX Architecture
VCCIO
PCI Clamp (4)
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–109