ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 11

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–2. Arria GX Transceiver Channel Block Diagram
Notes to
(1)
(2)
Altera Corporation
May 2008
Reference
Reference
PMA Analog Section
Clock
Clock
“n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.
n = 8 or 10.
“m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the
transceiver. m = 8, 10, 16, or 20.
Figure
Deserializer
Transmitter
Recovery
Serializer
Receiver
Clock
Unit
PLL
PLL
2–2:
(1)
(1)
n
n
PCS Digital Section
Aligner
Word
Figure 2–2
Each transceiver channel is full-duplex and consists of a transmitter
channel and a receiver channel.
The transmitter channel contains the following sub-blocks:
■
■
■
■
■
The receiver channel contains the following:
■
■
■
■
■
■
■
■
■
■
■
Deskew
XAUI
Lane
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
Receiver differential input buffer
Receiver lock detector and run length checker
Clock recovery unit (CRU)
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Receiver phase compensation FIFO buffer
Encoder
8B/10B
shows functional blocks that make up a transceiver channel.
Matcher
Rate
Decoder
8B/10B
Serializer
Byte
Deserializer
Byte
Arria GX Device Handbook, Volume 1
Compensation
FIFO Buffer
Arria GX Architecture
Phase
Compensation
FIFO Buffer
Phase
FPGA Fabric
(2)
(2)
m
m
2–3