ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 24

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
2–16
Arria GX Device Handbook, Volume 1
f
The clock recovery unit controls whether the receiver PLL locks to the
input reference clock (lock-to-reference mode) or the incoming serial data
(lock-to data mode). You can set the CRU to switch between lock-to-data
and lock-to-reference modes automatically or manually. In automatic
lock mode, the phase detector and dedicated parts per million (PPM)
detector within each receiver channel control the switch between
lock-to-data and lock-to-reference modes based on some pre-set
conditions. In manual lock mode, you control the switch manually using
the rx_locktorefclk and rx_locktodata signals.
For more details, refer to the Clock Recovery Unit section in the
Transceiver Protocol Support and Additional Features
the Arria GX Device Handbook.
Table 2–4
rx_locktorefclk and rx_locktodata signals.
If the rx_locktorefclk and rx_locktodata ports are not used, the
default is automatic lock mode.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer
using the high-speed serial recovered clock and deserializes into 8- or
10-bit parallel data using the low-speed parallel recovered clock. The
serial data is assumed to be received with LSB first, followed by MSB. It
feeds the deserialized 8- or 10-bit data to the word aligner, as shown in
Figure
Table 2–4. CRU Manual Lock Signals
rx_locktorefclk
2–14.
show the behavior of THE CRU block with respect to the
1
x
0
rx_locktodata
0
1
0
Lock-to-reference clock
Lock-to-data
Automatic
chapter in volume 2 of
CRU Mode
Altera Corporation
Arria GX
May 2008