ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 143

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Notes to
(1)
(2)
CONFIG_IO
Device
EP1AGX20
EP1AGX35
EP1AGX50
Table 3–1. Arria GX JTAG Instructions (Part 2 of 2)
Table 3–3. 2-Bit Arria GX Device IDCODE (Part 1 of 2)
JTAG Instruction
Bus hold and weak pull-up resistor features override the high-impedance state of
EXTEST
For more information about using the
Solution for Altera Devices
Table
.
(2)
3–1:
Version (4 Bits)
Instruction Code
00 0000 1101
0000
0000
0000
White Paper.
The Arria GX device instruction register length is 10 bits and the
USERCODE register length is 32 bits.
boundary-scan register length and device IDCODE information for
Arria GX devices.
Table 3–2. Arria GX Boundary-Scan Register Length
CONFIG_IO
Part Number (16 Bits)
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
Allows configuration of I/O standards through the JTAG chain
for JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during
configuration. Once issued, the
nSTATUS
held low until the IOE configuration register is loaded and the
TAP controller state machine transitions to the
state.
0010 0001 0010 0001
0010 0001 0010 0001
0010 0001 0010 0010
Device
instruction, refer to the
IDCODE (32 Bits)
low to reset the configuration device.
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Description
Tables 3–2
Arria GX Device Handbook, Volume 1
Manufacturer
Identity (11 Bits)
Boundary-Scan Register Length
000 0110 1110
000 0110 1110
000 0110 1110
MorphIO: An I/O Reconfiguration
CONFIG_IO
HIGHZ
and
3–3
1320
1320
1668
1668
2016
,
CLAMP
instruction holds
show the
UPDATE_DR
nSTATUS
LSB (1 Bit)
, and
1
1
1
is
3–3