ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 100

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

PLLs and Clock Networks
Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs
Note to
(1)
2–92
Arria GX Device Handbook, Volume 1
Clock Pins
CLK0p
CLK1p
CLK2p
CLK3p
Drivers from Internal Logic
Left Side Global & Regional Clock
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 1 of 3)
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
Network Connectivity
Figure
2–63:
PLL 7
PLL 8
Fast
Fast
C0
C1
C2
C3
C0
C1
C2
C3
RCLK0
RCLK4
v
v
RCLK1
RCLK5
v
v
RCLK2
RCLK6
v
v
RCLK3
RCLK7
v
v
v
GCLK0
v
GCLK1
v
GCLK2
v
GCLK3
v
Altera Corporation
v
v
May 2008
Note (1)
v