ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 23

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–13. Receiver PLL and Clock Recovery Unit
Notes to
(1)
(2)
Altera Corporation
May 2008
Inter-Transceiver Lines
REFCLK0
Dedicated
REFCLK1
Global Clock (2)
Dedicated
You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard
Plug-In Manager. Based on your selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the
necessary /M and /L dividers.
The global clock line must be driven from an input pin only.
Figure
[2:0]
2–13:
rx_locktorefclk
/2
/2
rx_locktodata
rx_datain
generates two clocks: a high-speed serial recovered clock that clocks the
deserializer and a low-speed parallel recovered clock that clocks the
receiver's digital logic.
Figure 2–13
The reference clock input to the receiver PLL can be derived from:
■
■
■
All the parameters listed are programmable in the Quartus II software.
The receiver PLL has the following features:
■
■
■
■
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Operates from 600 Mbps to 3.125 Gbps.
Uses a reference clock between 50 MHz and 622.08 MHz.
Programmable bandwidth settings: low, medium, and high.
Programmable rx_locktorefclk (forces the receiver PLL to lock
to reference clock) and rx_locktodata (forces the receiver PLL to
lock to data).
The voltage-controlled oscillator (V
Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and
25. Not all settings are supported for any particular frequency.
Two lock indication signals are provided. They are found in PFD
mode (lock-to-reference clock), and PD (lock-to-data).
shows a block diagram of the receiver PLL and CRU circuits.
rx_cruclk
Clock Recovery Unit ( CRU ) Control
PFD
up
dn
/M
up
dn
rx_pll_locked
Arria GX Device Handbook, Volume 1
CP+ LF
CO
) operates at half rate.
VCO
High-speed serial recovered clk
Low-speed parallel recovered clk
Arria GX Architecture
rx_freqlocked
/L
2–15