ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 103

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ep1agx50d

Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Figure 2–64. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL
Outputs
Note to
(1)
Altera Corporation
May 2008
If the design uses the feedback input, you will lose one (or two if FBIN is differential) external clock output pin.
Figure
Note (1)
2–64:
Regional
Regional
Clocks
Clocks
Clocks
Global
RCLK27
RCLK26
RCLK25
RCLK24
RCLK10
RCLK11
RCLK8
RCLK9
Figure 2–64
outputs and top and bottom CLK pins.
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
shows the global and regional clocking from enhanced PLL
PLL 11
PLL 12
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 5
PLL 6
Arria GX Device Handbook, Volume 1
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
RCLK12
RCLK13
RCLK14
RCLK15
Arria GX Architecture
2–95

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