ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 133

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Note to
(1)
484-pin FineLine BGA
780-pin FineLine GBA
484-pin FineLine BGA
Table 2–30. EP1AGX20 Device Differential Channels
Table 2–31. EP1AGX35 Device Differential Channels
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Package
Table
Package
2–30:
Transmitter
Receiver
Transmitter
Receiver
Transmitter/Receiver
channels that each fast PLL can drive in both I/O banks (I/O Bank 1 and
I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20
device, PLL 1 can drive a maximum of 16 transmitter channels in I/O
Bank 2 or a maximum of 29 transmitter channels in I/O Banks 1 and 2.
The Quartus II software can also merge receiver and transmitter PLLs
when a receiver is driving a transmitter. In this case, one fast PLL can
drive both the maximum numbers of receiver and transmitter channels.
1
Transmitter
Receiver
Transmitter/Receiver
For more details, refer to the Differential Pin Placement
Guidelines section in the
with DPA in Arria GX Devices
Device Handbook.
Total Channels
Note (1)
Note (1)
29
31
29
31
Total Channels
High-Speed Differential I/O Interfaces
Arria GX Device Handbook, Volume 1
chapter in volume 2 of the Arria GX
29
31
PLL1
16
13
17
14
16
13
17
14
Center Fast PLLs
Arria GX Architecture
PLL1
Center Fast PLLs
16
13
17
14
PLL2
13
16
14
17
13
16
14
17
PLL2
13
16
14
17
2–125