ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 32

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Transceivers
2–24
Arria GX Device Handbook, Volume 1
Figure 2–17
control indicator.
Figure 2–17. 10-Bit to 8-Bit Conversion
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups,
the 8B/10B decoder block asserts an error flag on the rx_errdetect
port. If the received 10-bit code is detected with incorrect running
disparity, the 8B/10B decoder block asserts an error flag on the
rx_disperr and rx_errdetect ports. The error flag signals
(rx_errdetect and rx_disperr) have the same data path delay from
the 8B/10B decoder to the PLD-transceiver interface as the bad code
group.
Receiver State Machine
The receiver state machine operates in Basic, GIGE, PCI Express (PIPE),
and XAUI modes. In GIGE mode, the receiver state machine replaces
invalid code groups with K30.7. In XAUI mode, the receiver state
machine translates the XAUI PCS code group to the XAUI XGMII code
group.
Byte Deserializer
Byte deserializer takes in one-byte wide data from the 8B/10B decoder
and deserializes it into a two-byte wide data at half the speed. This allows
clocking the PLD-receiver interface at half the speed as compared to the
receiver PCS logic. The byte deserializer is bypassed in GIGE mode.
MSB Received Last
shows a 10-bit code group decoded to an 8-bit data and a 1-bit
ctrl
9
j
h
8
H
7
g
7
G
6
6
8B/10B Conversion
f
5
F
5
i
E
4
e
4
D
3
d
3
2
C
c
2
1
B
LSB Received First
b
1
0
A
Altera Corporation
Parallel Data
a
0
May 2008