ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 59

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
Altera Corporation
May 2008
3-Bit Add Example
implemented in adders.
implemented in LUTs.
+
2nd stage add is
1st stage add is
1 1 0 1
1 1 0
+
Binary Add
1 1 0
1 0 1
0 1 0
0 0 1
+
R3 R2 R1 R0
C2 C1 C0
Shared Arithmetic Chain
In addition to dedicated carry chain routing, the shared arithmetic chain
available in shared arithmetic mode allows the ALM to implement a
three-input add, which significantly reduces the resources necessary to
implement large adder trees or correlator functions. Shared arithmetic
chains can begin in either the first or fifth ALM in a LAB. The Quartus II
Compiler automatically links LABs to create shared arithmetic chains
longer than 16 (8 ALMs in arithmetic or shared arithmetic mode). For
enhanced fitting, a long shared arithmetic chain runs vertically allowing
+
+
Equivalents
Decimal
X2 X1 X0
S2 S1 S0
2 x 6
Y2 Y1 Y0
Z2 Z1 Z0
+
13
6
5
2
1
X0
Y0
X1
Y1
X2
Y2
Z0
Z1
Z2
ALM Implementation
ALM 1
ALM 2
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Arria GX Device Handbook, Volume 1
S0
C0
S1
C1
S2
C2
shared_arith_in = '0'
'0'
carry_in = '0'
Arria GX Architecture
R0
R1
R2
R3
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