ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 268
ep1agx50d
Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1AGX50D.pdf
(296 pages)
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Maximum Input and Output Clock Toggle Rate
4–114
Arria GX Device Handbook, Volume 1
To calculate the output toggle rate for a non 0 pF load, use this formula:
The toggle rate for a non 0 pF load
For example, the output toggle rate at 0 pF load for SSTL-18 Class II
20 mA I/O standard is 550 MHz on a -3 device clock output pin. The
derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated
as:
Table 4–102
device column I/O pins.
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
3.3-V PCI
3.3-V PCI-X
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
= 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load
value in pF /1,000)
1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz)
I/O Standards
shows the maximum input clock toggle rates for Arria GX
-6 Speed Grade
420
420
420
420
420
467
467
467
467
467
467
467
467
420
420
Altera Corporation
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
May 2008
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