ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 145

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
May 2008
Operating Modes
The Arria GX architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allows you to reconfigure Arria GX
devices in-circuit by loading new configuration data into the device. With
real-time reconfiguration, the device is forced into command mode with
a device pin. The configuration process loads different configuration
data, re-initializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
PORSEL is a dedicated input pin used to select power-on reset (POR)
delay times of 12 ms or 100 ms during power up. When the PORSEL pin
is connected to ground, the POR time is 100 ms. When the PORSEL pin is
connected to V
The nIO_PULLUP pin is a dedicated input that chooses whether the
internal pull-up resistors on the user I/O pins and dual-purpose
configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY,
nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR)
are on or off before and during configuration. A logic high (1.5, 1.8, 2.5,
3.3 V) turns off the weak internal pull-up resistors, while a logic low turns
them on.
Arria GX devices also offer a new power supply, V
connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on
the configuration input pins and JTAG pins. V
input pins (TCK, TMS, TDI, and TRST) and the following configuration
pins: nCONFIG, DCLK (when used as an input), nIO_PULLUP,
DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The V
pin allows the V
reside) to be independent of the voltage required by the configuration
inputs. Therefore, when selecting the V
take the VIL and VIH levels driven to the configuration inputs into
consideration. The configuration input pins, nCONFIG, DCLK (when used
as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR,
have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V
CC
CCIO
, the POR time is 12 ms.
setting (of the banks where the configuration inputs
Arria GX Device Handbook, Volume 1
CCIO
voltage, you do not have to
CCPD
applies to all the JTAG
CCPD
, which must be
Configuration
CCSEL
3–5