ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 197

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Typical Design
Performance
Altera Corporation
May 2008
The following section describes the typical design performance for the
Arria GX device family.
User I/O Pin Timing
Tables 4–48
buffer t
by a non-PLL global clock (GCLK) and a PLL driven global clock
(GCLK-PLL). For t
the adder tables listed for each device to the GCLK/GCLK-PLL values for
the device.
EP1AGX20 I/O Timing Parameters
Tables 4–48
EP1AGX20 devices for I/O standards which support general purpose
I/O pins.
Table 4–48
clock in Arria GX devices.
1.8-V differential HSTL Class II
LVDS
RCLK
adder
RCLK
input adder
RCLK
adder
RCLK
output adder
Table 4–47. Default Loading of Different I/O Standards for Arria GX
Devices (Part 2 of 2)
Table 4–48. EP1AGX20 Row Pin Delay Adders for Regional Clock
Parameter
input
PLL
PLL
SU
output
, t
describes the row pin delay adders when using the regional
H
to
through
, and t
I/O Standard
4–77
Industrial
SU
CO
-0.117
-0.011
0.117
0.011
show user I/O pin timing for Arria GX devices. I/O
, t
4–51
are reported for the cases when I/O clock is driven
H
, and t
Fast Corner
show the maximum I/O timing parameters for
CO
Commercial
using regional clock, add the value from
-0.117
-0.011
0.117
0.011
Arria GX Device Handbook, Volume 1
DC and Switching Characteristics
Capacitive Load
-6 Speed
-0.273
-0.019
Grade
0.273
0.019
0
0
Units
ns
ns
ns
ns
Unit
pF
pF
4–43