ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 115

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration
Notes to
(1)
(2)
Altera Corporation
May 2008
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–72:
clkout
clkin
oe
ce_out
aclr/apreset
ce_in
sclr/spreset
Chip-Wide Reset
The Arria GX device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
Output Register
Input Register
OE Register
D
CLRN/PRN
ENA
ENA
D
CLRN/PRN
D
CLRN/PRN
ENA
Q
Q
Q
Note (1)
Drive Strength Control
Open-Drain Output
Pin Delay
Output
Input Register Delay
Logic Array Delay
Arria GX Device Handbook, Volume 1
Input Pin to
Input Pin to
OE Register
t
CO
Delay
V
Arria GX Architecture
CCIO
PCI Clamp (2)
V
CCIO
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–107