ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 282

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Duty Cycle Distortion
4–128
Arria GX Device Handbook, Volume 1
Note to
(1)
Note to
(1)
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
LVPECL
DDIO Column Output I/O
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path (Part 2 of 2)
Note (1)
Table 4–111. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path
Maximum DCD (ps) for
Maximum DCD (ps) for
Row DDIO Output I/O
Table 4–110
Table 4–111
Table
Table
Standard
Standard
4–110:
4–111:
assumes the input clock has zero DCD.
assumes the input clock has zero DCD.
3.3/2.5V
3.3/2.5V
350
335
330
330
180
440
390
375
325
430
355
350
335
320
330
330
330
330
180
TTL/CMOS
TTL/CMOS
Input IO Standard (No PLL in the Clock Path)
Input I/O Standard (No PLL in the Clock Path)
1.8/1.5V
405
390
385
390
180
1.8/1.5V
495
450
430
385
490
410
405
390
375
385
385
390
360
180
SSTL-2
2.5V
180
80
65
60
60
SSTL-2
2.5V
170
120
105
160
180
90
85
80
65
70
60
60
60
90
SSTL/HSTL
1.8/1.5V
180
70
65
70
70
SSTL/HSTL
1.8/1.5V
100
180
160
110
100
155
95
75
70
65
80
70
70
70
Altera Corporation
LVDS
3.3V
105
110
105
180
90
May 2008
Note (1)
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Unit
ps
ps
ps
ps
ps