ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 138

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

High-Speed Differential I/O with DPA Support
Figure 2–81. Fast PLL and Channel Layout in the EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D
Devices
Note to
(1)
2–130
Arria GX Device Handbook, Volume 1
See
Figure
Table 2–30
Note (1)
2–81:
4
for the number of channels each device supports.
2
2
4
4
For high-speed source synchronous interfaces such as POS-PHY 4 and the
Parallel RapidIO standard, the source synchronous clock rate is not a
byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols since the source synchronous clock does not
provide a byte or word boundary since the clock is one half the data rate,
not one eighth. The Arria GX device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for
user-controlled byte boundary shifting. This simplifies designs while
saving ALM resources. You can use an ALM-based state machine to
signal the shift of receiver byte boundaries until a specified pattern is
detected to indicate byte alignment.
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left side of the device has one receiver channel and one
transmitter channel per LAB row.
channel layout in the EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D and
EP1AGX60C/D devices.
layout in EP1AGX60E and EP1AGX90E devices.
PLL 1
PLL 2
Fast
Fast
LVDS
LVDS
Clock
Clock
Clock
Clock
DPA
DPA
Figure 2–82
Quadrant
Quadrant
Figure 2–81
shows the fast PLL and channel
shows the fast PLL and
Quadrant
Quadrant
Altera Corporation
May 2008