ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 288

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

External Memory Interface Specifications
External
Memory
Interface
Specifications
4–134
Arria GX Device Handbook, Volume 1
Note to
(1)
t
t
ARESET
ARESET_RECONFIG
Table 4–117. Fast PLL Specifications (Part 2 of 2)
This is limited by the I/O f
Name
Table
4–117:
Minimum pulse width on
Minimum pulse width on the
when using PLL reconfiguration. Reset the
PLL after
Tables 4–118
dedicated circuitry used for interfacing with external memory devices.
MAX
Notes to
(1)
(2)
Number of DQS Delay Buffer Stages
scandone
Table 4–118. DLL Frequency Range Specifications
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (t
Note (1)
.
Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
Description
Table
Frequency Mode
goes high.
through
4–119:
areset
(2)
1
2
3
4
areset
0
1
2
4–122
signal.
signal
contain Arria GX device specifications for the
Min
500
10
Commercial (ps)
110
130
160
80
Frequency Range (MHz)
Typ
100 to 175
150 to 230
200 to 310
Altera Corporation
Industrial (ps)
Max
DQS_JITTER
110
130
180
210
May 2008
Unit
ns
ns
) ,