ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 187

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ep1agx50d

Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Altera Corporation
May 2008
50-Ω R
1.5
50-Ω R
1.2
25-Ω R
3.3/2.5
50-Ω R
3.3/2.5/1.8
50-Ω R
R
C
C
C
C
C
Table 4–40. Series On-Chip Termination Specification for Top and Bottom I/O Banks (Part 2 of 2)
Table 4–41. Series On-Chip Termination Specification for Left I/O Banks
Table 4–42. Arria GX Device Capacitance
Symbol
D
IOTB
IOL
CLKTB
CLKL
CLKL+
Symbol
Symbol
S
S
S
S
S
1.5
Internal series termination without
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed
differential receiver and transmitter pins.
Input capacitance on top/bottom clock input pins:
CLK[12..15]
Input capacitance on left clock inputs:
Input capacitance on left clock inputs:
Internal series termination without
calibration (25-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal differential termination for
LVDS (100-Ω setting)
Description
Description
Pin Capacitance
Table 4–42
.
shows the Arria GX device family pin capacitance.
Parameter
Note (1)
V
V
CLK0
CLK1
Conditions
CCIO
CCIO
V
(Part 1 of 2)
CCIO
V
CCIO
V
= 1.5V
= 1.2V
V
Conditions
and
and
CCIO
CCIO
= 3.3/2.5/1.8V
= 3.3/2.5V
CLK2
CLK3
= 3.3 V
CLK[4..7]
= 1.5V
.
.
Commercial
Arria GX Device Handbook, Volume 1
DC and Switching Characteristics
Max
±36
±50
and
Commercial
Resistance Tolerance
Max
±30
±30
±36
±20
Resistance Tolerance
Industrial
Max
±36
±50
Industrial
Typical
5.0
6.1
6.0
6.1
3.3
Max
±30
±30
±36
±25
Unit
Unit
Unit
%
%
pF
pF
pF
pF
pF
%
%
%
%
4–33

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