ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 137

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–80. GX Receiver Channel
Altera Corporation
May 2008
Up to 840 Mbps
Eight Phase Clocks
+
–
refclk
f
data
Fast
PLL
8
retimed_data
DPA
Figure 2–80
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the V
to the DPA circuitry.
For more information about fast PLL, see the
chapter in volume 2 of the Arria GX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of
channel-to-channel or clock-to-channel skew. The DPA block locks to a
phase closest to the serial data phase. The phase-aligned DPA clock is
used to write the data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
DPA_clk
shows the block diagram of the Arria GX receiver channel.
Synchronizer
diffioclk
load_en
D
Q
Data Realignment
Circuitry
Arria GX Device Handbook, Volume 1
Dedicated
Interface
Receiver
PLLs in Arria GX Devices
Arria GX Architecture
Data to R4, R24, C4, or
direct link interconnect
Regional or
global clock
10
CO
can feed
2–129