ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 148

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Configuration and Testing
3–8
Arria GX Device Handbook, Volume 1
f
microprocessor and flash memory), AS, and PS configuration schemes.
Decompression is not supported in the PPA configuration scheme nor in
JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in
remote locations are difficult challenges faced by system designers.
Arria GX devices can help effectively deal with these challenges with
their inherent re programmability and dedicated circuitry to perform
remote system updates. Remote system updates help deliver feature
enhancements and bug fixes without costly recalls, reduce time to
market, and extend product life.
Arria GX FPGAs feature dedicated remote system upgrade circuitry to
facilitate remote system updates. Soft logic (Nios
implemented in the Arria GX device can download a new configuration
image from a remote location, store it in configuration memory, and direct
the dedicated remote system upgrade circuitry to initiate a
reconfiguration cycle. The dedicated circuitry performs error detection
during and after the configuration process, recovers from any error
condition by reverting back to a safe configuration image, and provides
error status information. This dedicated remote system upgrade circuitry
avoids system downtime and is the critical component for successful
remote system upgrades.
Remote system configuration is supported in the following Arria GX
configuration schemes: FPP, AS, PS, and PPA. You can also implement
remote system configuration in conjunction with Arria GX features such
as real-time decompression of configuration data for efficient field
upgrades.
For more information about remote configuration in Arria GX devices,
refer to the
volume 2 of the Arria GX Device Handbook.
Configuring Arria GX FPGAs with JRunner
The JRunner software driver configures Altera FPGAs, including
Arria GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables in
JTAG mode. The programming input file supported is in Raw Binary File
(.rbf) format. JRunner also requires a Chain Description File (.cdf)
generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on other platforms.
Remote System Upgrades with Arria GX Devices
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processor or user logic)
Altera Corporation
chapter in
May 2008